Basic PLDs (programmable logic devices) are based on a programmable logic array, normally composed of a specific number of input lines connected through a fixed or programmable array to the input terminals of a set of AND logic gates, the output terminals of which are in turn connected to the input terminals of a fixed or programmable array of OR gates. Devices are called PAL.RTM.-based when the Programmable Array Logic has a fixed OR array. The size (number of gates) of the programmable array and the size (complexity) of the highly configurable associated I/O (input/output) macrocells has been increased recently over that of the basic PLD architecture to meet the requirements of complex logic functions and high configurability.
Recently, new kinds of PAL-based devices (chips) have appeared, such as the Altera Max family, AMD Mach family and XILINX EPLD devices that feature on each chip functional blocks which are structurally and functionally identical and have a programmable interconnect resource which interconnects the functional blocks. Such an interconnect is designated the programmable interconnect array (PIA) in the Altera Max family, the Switch Matrix in the AMD Mach family, and the Universal Interconnect matrix (UIM) in the XILINX XC7236 device. Each functional block on the chips mentioned includes a programmable AND array and several macrocells so that it is like a stand alone PAL, and upon appropriate configuration can be used logically separate from the rest of the chip or can communicate with the rest of the chip.
FIG. 1 illustrates in simplified form the architecture of the XILINX XC7236 chip, a PAL-based EPLD. Four configurable functional blocks FB1, FB2, FB3, FB4 are interconnected by a central universal interconnect matrix (UIM). Each of the four blocks FB1-FB4 receives 21 input lines from the UIM, and connects by nine output lines to chip I/O pads labelled "I/O" and/or back into the UIM. Blocks FB2, FB3, FB4 receive 3 input lines coming from the I/O pads as well. Each block FB-1-FB-4 has carry-in and carry-out lines as well as shift-in and shift-out lines, with the in lines of each block being connected to the out lines of a previous block and the out lines of each block being connected to the in lines of a next block, forming loops as illustrated around the blocks. Each of the functional blocks FB1-FB4 includes nine macrocells (not shown) and a programmable AND array (not shown) which is driven by 21 input lines from the UIM and three input lines coming directly from the I/O pads (for three blocks only in the case of the XC7236). The XC7236 device thus contains 36 macrocells each having identical structure.
FIG. 2 shows the schematic diagram of one of the macrocells and the AND array present in each functional block of the XC7236 chip. Macrocells MC1-MC9 in each block (FIG. 2 shows MC1 only) are driven by the product terms (P-terms) derived from the programmable AND array AA2 in the same block. Five P-terms PP1-PP5, PP6-PP10 . . . PP41-PP45 are private to each macrocell in the block, while an additional twelve P-terms SP1-SP12 are shared among the nine macrocells in each block. Four of the private P-terms PP1-PP4 can be selectively (through programming of programmable switch elements SW1-SW4) logically ORed by gate OR1 together with up to four shared P-terms SP9-SP12 and drive the D1 data input terminal of an arithmetic logic unit ALU. The other data input terminal D2 of the ALU is driven by the output signal of gate OR2 which logically ORs the fifth private P-term PP5 and up to eight of the remaining shared P-terms SP1-SP8. The four private P-terms PP1-PP4 can be programmed for other purposes; for instance the private P-term PP1 can be used as a dedicated clock signal for the flip-flop FF; P-term PP2 can be the output enable signal OE; P-term PP3 and P-term PP4 can be the asynchronous SET S and RESET R signals for the flip-flop FF.
The ALU can be programmed into two modes, logic mode and arithmetic mode. In the logic mode, the ALU is a 2-input function generator that can be programmed to generate any Boolean function of its two data input terminals D1 and D2. In the arithmetic mode, the ALU can be programmed to generate the arithmetic sum or difference of two operands, combined with a carry signal coming from the next lower order macrocell and feeds a carry output to the next higher order macrocell as well.
The ALU output F drives the D input terminal of the flip-flop FF. Flip-flop FF can be programmed by configuration bit CB6 to be transparent, making the output signal on terminal Q identical with the D terminal input signal, independent of the clock input signal, or to operate in the conventional flip-flop manner, triggered by the rising edge of the clock input signal. The clock signal source is programmable by programming of configuration bits CB3 and CB4 to select (via multiplexer MUX2) either the dedicated P-term PP1, or one of two global clock signals FLCK0 and FLCK1.
The output signal on terminal Q of flip flop FF can be optionally fed back and logically ORed into the input terminal D2 of the ALU after being logically ANDed with three shared P-terms SP1-SP3 by programming of the configuration bits CB1 and CB2. The polarity of the feedback signal can be controlled by the gate XOR by programming the configuration bit CB7.
A logic block with macrocells of this kind is both complex and highly configurable and can implement a variety of logic functions by programming of the configuration bits such as CB1-CB7, switches such as SW1-SW16, tri-state buffers such as TSB1 and TSB2, and multiplexers in the ALU. However, such high configurability requires a large number of logic gates in the speed path, which causes additional propagation delay. This, together with the delay caused by routing signals through the UIM limits the speed of such devices. High speed and high flexibility of logic functions are generally in conflict with each other and must be traded off in such prior art devices. So far, no devices exist that can offer both high speed and high flexibility of logic functions for user applications.
Some prior art FPGA devices include different kinds of blocks that are optimized for different applications. For example, the Actel ACT2 chip family has two types of logic blocks, a logic block for combinatorial functions and a logic block for both combinatorial and register functions. The two logic block types use common routing resources, and all blocks have their I/O routed via the common interconnect. These FPGAs do not have special sections of the chip with their own internal routing resources that optimize that particular section for speed or complexity.